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[PULL 09/18] riscv/sifive_u: Manually define the machine
From: |
Palmer Dabbelt |
Subject: |
[PULL 09/18] riscv/sifive_u: Manually define the machine |
Date: |
Mon, 28 Oct 2019 08:48:53 -0700 |
From: Alistair Francis <address@hidden>
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to specify machine properties.
This patch is no functional change.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++-----------
include/hw/riscv/sifive_u.h | 7 +++++-
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a32d6773a8..eb4124f5b4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -311,8 +311,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
static void riscv_sifive_u_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
-
- SiFiveUState *s = g_new0(SiFiveUState, 1);
+ SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
@@ -434,6 +433,10 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
+static void riscv_sifive_u_machine_instance_init(Object *obj)
+{
+}
+
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -547,17 +550,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
-static void riscv_sifive_u_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
- mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
- mc->default_cpus = mc->min_cpus;
-}
-
-DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -581,3 +573,29 @@ static void riscv_sifive_u_soc_register_types(void)
}
type_init(riscv_sifive_u_soc_register_types)
+
+static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = riscv_sifive_u_init;
+ mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+}
+
+static const TypeInfo riscv_sifive_u_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_u"),
+ .parent = TYPE_MACHINE,
+ .class_init = riscv_sifive_u_machine_class_init,
+ .instance_init = riscv_sifive_u_machine_instance_init,
+ .instance_size = sizeof(SiFiveUState),
+};
+
+static void riscv_sifive_u_machine_init_register_types(void)
+{
+ type_register_static(&riscv_sifive_u_machine_typeinfo);
+}
+
+type_init(riscv_sifive_u_machine_init_register_types)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 0062276190..794b958dcc 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState {
CadenceGEMState gem;
} SiFiveUSoCState;
+#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
+#define RISCV_U_MACHINE(obj) \
+ OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
+
typedef struct SiFiveUState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
SiFiveUSoCState soc;
+
void *fdt;
int fdt_size;
} SiFiveUState;
--
2.21.0
- [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Palmer Dabbelt, 2019/10/28
- [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode, Palmer Dabbelt, 2019/10/28
- [PULL 02/18] RISC-V: Handle bus errors in the page table walker, Palmer Dabbelt, 2019/10/28
- [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed, Palmer Dabbelt, 2019/10/28
- [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node, Palmer Dabbelt, 2019/10/28
- [PULL 06/18] linux-user/riscv: Propagate fault address, Palmer Dabbelt, 2019/10/28
- [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes, Palmer Dabbelt, 2019/10/28
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory, Palmer Dabbelt, 2019/10/28
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine,
Palmer Dabbelt <=
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak, Palmer Dabbelt, 2019/10/28
- [PULL 18/18] target/riscv: PMP violation due to wrong size parameter, Palmer Dabbelt, 2019/10/28
- Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Peter Maydell, 2019/10/29