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[PULL 02/18] RISC-V: Handle bus errors in the page table walker
From: |
Palmer Dabbelt |
Subject: |
[PULL 02/18] RISC-V: Handle bus errors in the page table walker |
Date: |
Mon, 28 Oct 2019 08:48:46 -0700 |
We directly access physical memory while walking the page tables on
RISC-V, but while doing so we were using cpu_ld*() which does not report
bus errors. This patch converts the page table walker over to use
address_space_ld*(), which allows bus errors to be detected.
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6ece..c82e7ed52b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
* (riscv_cpu_do_interrupt) is correct */
-
+ MemTxResult res;
+ MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
@@ -256,11 +257,16 @@ restart:
1 << MMU_DATA_LOAD, PRV_S)) {
return TRANSLATE_PMP_FAIL;
}
+
#if defined(TARGET_RISCV32)
- target_ulong pte = ldl_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
#elif defined(TARGET_RISCV64)
- target_ulong pte = ldq_phys(cs->as, pte_addr);
+ target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
#endif
+ if (res != MEMTX_OK) {
+ return TRANSLATE_FAIL;
+ }
+
hwaddr ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
--
2.21.0
- [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Palmer Dabbelt, 2019/10/28
- [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode, Palmer Dabbelt, 2019/10/28
- [PULL 02/18] RISC-V: Handle bus errors in the page table walker,
Palmer Dabbelt <=
- [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed, Palmer Dabbelt, 2019/10/28
- [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node, Palmer Dabbelt, 2019/10/28
- [PULL 06/18] linux-user/riscv: Propagate fault address, Palmer Dabbelt, 2019/10/28
- [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes, Palmer Dabbelt, 2019/10/28
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory, Palmer Dabbelt, 2019/10/28
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28