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Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device |
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Date: |
Thu, 30 May 2019 11:57:12 +0100 |
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt <address@hidden> wrote:
>
> From: Fabien Chouteau <address@hidden>
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as both output and input.
>
> Signed-off-by: Fabien Chouteau <address@hidden>
> Reviewed-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Hi; this patch causes Coverity to complain about a memory
leak (CID 1401707):
> static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> + Error *err = NULL;
>
> SiFiveESoCState *s = RISCV_E_SOC(dev);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -184,8 +188,28 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
> Error **errp)
> sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
> - memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
> +
> + /* GPIO */
> +
> + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
This function allocated xip_mem and mask_rom via g_new() but
then this error-exit doesn't free them.
The best way to fix this is to stop doing separate memory
allocations at all -- instead just have fields in the
SiFiveESoCState struct
MemoryRegion xip_mem;
Memory_Region mask_rom;
and pass &s->xip_mem etc where currently the code uses xip_mem.
thanks
-- PMM
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, (continued)
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device,
Peter Maydell <=
- [Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28