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[Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all o
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats |
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Date: |
Sat, 25 May 2019 18:09:23 -0700 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn32.decode | 10 +++++++---
target/riscv/translate.c | 18 ++++++++++++++++++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52d3..77f794ed703d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,9 +34,13 @@
%imm_u 12:s20 !function=ex_shift_12
# Argument sets:
+&empty
&b imm rs2 rs1
&i imm rs1 rd
+&j imm rd
&r rd rs1 rs2
+&s imm rs1 rs2
+&u imm rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -44,9 +48,9 @@
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1
%rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1
%rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
address@hidden ....... ..... ..... ... ..... ....... imm=%imm_s
%rs2 %rs1
address@hidden .................... ..... ....... imm=%imm_u
%rd
address@hidden .................... ..... ....... imm=%imm_j
%rd
address@hidden ....... ..... ..... ... ..... ....... &s imm=%imm_s
%rs2 %rs1
address@hidden .................... ..... ....... &u imm=%imm_u
%rd
address@hidden .................... ..... ....... &j imm=%imm_j
%rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1
%rd
@csr ............ ..... ... ..... ....... %csr %rs1
%rd
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 840ecbef36e7..928374242e83 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -687,11 +687,29 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
+/*
+ * Auto-generated decoder.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * initially declared by the 32-bit decoder, which results in duplicate
+ * declaration warnings. Suppress them.
+ */
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif
+
bool decode_insn16(DisasContext *ctx, uint16_t insn);
/* auto-generated decoder*/
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif
+
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
--
2.21.0
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, (continued)
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28