[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a commen
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment |
Date: |
Sat, 25 May 2019 18:09:32 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
linux-user/riscv/target_elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h
index a6716a6aac23..9dd65652ee45 100644
--- a/linux-user/riscv/target_elf.h
+++ b/linux-user/riscv/target_elf.h
@@ -9,6 +9,7 @@
#define RISCV_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
+ /* TYPE_RISCV_CPU_ANY */
return "any";
}
#endif
--
2.21.0
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, (continued)
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25