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[Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_h
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv |
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Date: |
Sat, 25 May 2019 18:09:31 -0700 |
From: Jonathan Behrens <address@hidden>
Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fc4c6b306e13..352646303420 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -29,7 +29,6 @@
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
--
2.21.0
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, (continued)
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28