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Re: [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag
From: |
David Gibson |
Subject: |
Re: [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag |
Date: |
Sun, 5 Jul 2020 19:07:54 +1000 |
On Wed, Jul 01, 2020 at 06:43:36PM -0500, Lijun Pan wrote:
> This flag will be used for Power10 instructions.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
>
> target/ppc/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 1988b436cb..a5e9c08dcc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2191,6 +2191,8 @@ enum {
> PPC2_PM_ISA206 = 0x0000000000040000ULL,
> /* POWER ISA 3.0
> */
> PPC2_ISA300 = 0x0000000000080000ULL,
> + /* POWER ISA 3.1
> */
> + PPC2_ISA310 = 0x0000000000100000ULL,
>
> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX |
> \
> PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions, Lijun Pan, 2020/07/01
- [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, Lijun Pan, 2020/07/01
- [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1, Lijun Pan, 2020/07/01
- [PATCH v4 05/11] target/ppc: add vmulld instruction, Lijun Pan, 2020/07/01
- [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions, Lijun Pan, 2020/07/01
- [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag, Lijun Pan, 2020/07/01
- Re: [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag,
David Gibson <=
- [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions, Lijun Pan, 2020/07/01
- [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition, Lijun Pan, 2020/07/01
[PATCH v4 09/11] fix the prototype of muls64/mulu64, Lijun Pan, 2020/07/01
[PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case, Lijun Pan, 2020/07/01