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Re: [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions
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From: |
Lijun Pan |
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Subject: |
Re: [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions |
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Date: |
Mon, 13 Jul 2020 14:35:58 -0500 |
> On Jul 1, 2020, at 6:43 PM, Lijun Pan <ljp@linux.ibm.com> wrote:
>
> vmulhsw: Vector Multiply High Signed Word
> vmulhuw: Vector Multiply High Unsigned Word
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> v3: inline the helper_vmulh{su}w multiply directly instead of using macro
> v2: fix coding style
> use Power ISA 3.1 flag
>
any feedback on this one?
- [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions, Lijun Pan, 2020/07/01
- [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, Lijun Pan, 2020/07/01
- [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1, Lijun Pan, 2020/07/01
- [PATCH v4 05/11] target/ppc: add vmulld instruction, Lijun Pan, 2020/07/01
- [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions, Lijun Pan, 2020/07/01
- Re: [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions,
Lijun Pan <=
- [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag, Lijun Pan, 2020/07/01
- [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions, Lijun Pan, 2020/07/01
- [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition, Lijun Pan, 2020/07/01
[PATCH v4 09/11] fix the prototype of muls64/mulu64, Lijun Pan, 2020/07/01