[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 63/68] util/cpuinfo-riscv: Detect Zbs
From: |
Richard Henderson |
Subject: |
[PULL 63/68] util/cpuinfo-riscv: Detect Zbs |
Date: |
Fri, 17 Jan 2025 10:24:51 -0800 |
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250102181601.1421059-2-richard.henderson@linaro.org>
---
host/include/riscv/host/cpuinfo.h | 5 +++--
util/cpuinfo-riscv.c | 18 ++++++++++++++++--
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/host/include/riscv/host/cpuinfo.h
b/host/include/riscv/host/cpuinfo.h
index cdc784e7b6..b2b53dbf62 100644
--- a/host/include/riscv/host/cpuinfo.h
+++ b/host/include/riscv/host/cpuinfo.h
@@ -9,8 +9,9 @@
#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
#define CPUINFO_ZBA (1u << 1)
#define CPUINFO_ZBB (1u << 2)
-#define CPUINFO_ZICOND (1u << 3)
-#define CPUINFO_ZVE64X (1u << 4)
+#define CPUINFO_ZBS (1u << 3)
+#define CPUINFO_ZICOND (1u << 4)
+#define CPUINFO_ZVE64X (1u << 5)
/* Initialized with a constructor. */
extern unsigned cpuinfo;
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
index 971c924012..0291b7218a 100644
--- a/util/cpuinfo-riscv.c
+++ b/util/cpuinfo-riscv.c
@@ -36,7 +36,8 @@ static void sigill_handler(int signo, siginfo_t *si, void
*data)
/* Called both as constructor and (possibly) via other constructors. */
unsigned __attribute__((constructor)) cpuinfo_init(void)
{
- unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND |
CPUINFO_ZVE64X;
+ unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS
+ | CPUINFO_ZICOND | CPUINFO_ZVE64X;
unsigned info = cpuinfo;
if (info) {
@@ -50,6 +51,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
#if defined(__riscv_arch_test) && defined(__riscv_zbb)
info |= CPUINFO_ZBB;
#endif
+#if defined(__riscv_arch_test) && defined(__riscv_zbs)
+ info |= CPUINFO_ZBS;
+#endif
#if defined(__riscv_arch_test) && defined(__riscv_zicond)
info |= CPUINFO_ZICOND;
#endif
@@ -71,7 +75,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
&& pair.key >= 0) {
info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0;
info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0;
- left &= ~(CPUINFO_ZBA | CPUINFO_ZBB);
+ info |= pair.value & RISCV_HWPROBE_EXT_ZBS ? CPUINFO_ZBS : 0;
+ left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS);
#ifdef RISCV_HWPROBE_EXT_ZICOND
info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0;
left &= ~CPUINFO_ZICOND;
@@ -117,6 +122,15 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
left &= ~CPUINFO_ZBB;
}
+ if (left & CPUINFO_ZBS) {
+ /* Probe for Zbs: bext zero,zero,zero. */
+ got_sigill = 0;
+ asm volatile(".insn r 0x33, 5, 0x24, zero, zero, zero"
+ : : : "memory");
+ info |= got_sigill ? 0 : CPUINFO_ZBS;
+ left &= ~CPUINFO_ZBS;
+ }
+
if (left & CPUINFO_ZICOND) {
/* Probe for Zicond: czero.eqz zero,zero,zero. */
got_sigill = 0;
--
2.43.0
- [PULL 44/68] tcg: Drop implementation checks from tcg-opc.h, (continued)
- [PULL 44/68] tcg: Drop implementation checks from tcg-opc.h, Richard Henderson, 2025/01/17
- [PULL 46/68] tcg/mips: Expand bswap unconditionally, Richard Henderson, 2025/01/17
- [PULL 50/68] tcg/aarch64: Expand extract with offset 0 with andi, Richard Henderson, 2025/01/17
- [PULL 52/68] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 53/68] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 57/68] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 58/68] tcg/sparc64: Use SRA, SRL for {s}extract_i64, Richard Henderson, 2025/01/17
- [PULL 49/68] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid, Richard Henderson, 2025/01/17
- [PULL 47/68] tcg/i386: Handle all 8-bit extensions for i686, Richard Henderson, 2025/01/17
- [PULL 64/68] tcg/riscv: Use BEXTI for single-bit extractions, Richard Henderson, 2025/01/17
- [PULL 63/68] util/cpuinfo-riscv: Detect Zbs,
Richard Henderson <=
- [PULL 62/68] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}, Richard Henderson, 2025/01/17
- [PULL 51/68] tcg/arm: Add full [US]XT[BH] into {s}extract, Richard Henderson, 2025/01/17
- [PULL 54/68] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 56/68] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64, Richard Henderson, 2025/01/17
- [PULL 60/68] tcg/tci: Remove assertions for deposit and extract, Richard Henderson, 2025/01/17
- [PULL 55/68] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 66/68] tcg: Document tb_lookup() and tcg_tb_lookup(), Richard Henderson, 2025/01/17
- [PULL 61/68] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}, Richard Henderson, 2025/01/17
- [PULL 67/68] accel/tcg: Call tcg_tb_insert() for one-insn TBs, Richard Henderson, 2025/01/17
- [PULL 59/68] tcg/tci: Provide TCG_TARGET_{s}extract_valid, Richard Henderson, 2025/01/17