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[PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper |
Date: |
Sun, 12 Jan 2025 23:16:45 +0100 |
For a particular physical address within the EthLite MMIO range,
addr_to_port_index() returns which port is accessed.
txbuf_ptr() points to the beginning of a (RAM) TX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-10-philmd@linaro.org>
---
hw/net/xilinx_ethlite.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 442467abeb8..8df621904a1 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -27,6 +27,7 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
+#include "qemu/bitops.h"
#include "qom/object.h"
#include "qapi/error.h"
#include "exec/tswap.h"
@@ -87,6 +88,18 @@ static inline void eth_pulse_irq(XlnxXpsEthLite *s)
}
}
+static unsigned addr_to_port_index(hwaddr addr)
+{
+ return extract64(addr, 11, 1);
+}
+
+static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index)
+{
+ unsigned int rxbase = port_index * (0x800 / 4);
+
+ return &s->regs[rxbase + R_TX_BUF0];
+}
+
static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
@@ -119,6 +132,7 @@ eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XlnxXpsEthLite *s = opaque;
+ unsigned int port_index = addr_to_port_index(addr);
unsigned int base = 0;
uint32_t value = val64;
@@ -132,12 +146,12 @@ eth_write(void *opaque, hwaddr addr,
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
- (void *) &s->regs[base],
+ txbuf_ptr(s, port_index),
s->regs[base + R_TX_LEN0]);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
- memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
+ memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
--
2.47.1
- [PULL 00/49] Misc HW patches for 2025-01-12, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 01/49] pc-bios/meson.build: Silent unuseful DTC warnings, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 02/49] target: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 05/49] hw/usb: Inline usb_try_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 04/49] hw: Add QOM parentship relation with CPUs, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 03/49] hw: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 07/49] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 06/49] hw/usb: Inline usb_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper,
Philippe Mathieu-Daudé <=
- [PULL 10/49] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 11/49] hw/net/xilinx_ethlite: Access TX_GIE register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 12/49] hw/net/xilinx_ethlite: Access TX_LEN register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 13/49] hw/net/xilinx_ethlite: Access TX_CTRL register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 14/49] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 15/49] hw/net/xilinx_ethlite: Map TX_LEN as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 16/49] hw/net/xilinx_ethlite: Map TX_GIE as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 17/49] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 18/49] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 19/49] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container', Philippe Mathieu-Daudé, 2025/01/12