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Re: [PULL 04/49] hw: Add QOM parentship relation with CPUs
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From: |
Zhao Liu |
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Subject: |
Re: [PULL 04/49] hw: Add QOM parentship relation with CPUs |
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Date: |
Tue, 14 Jan 2025 22:38:30 +0800 |
> I this specific case, one basically replaces /machine/unattached
> orphanage with explicit /machine one and many 'cpuN' children,
> which ain't any better than device[N].
>
> and in future I can imagine that at least in x86 case vcpus
> might have another parent depending on configuration.
> (i.e. being parented to cores instead)
I remember that this was your idea all along, and I'm not sure if you're
also referring to my previous patches about hybrid topology :-), which I'll
continue to refresh afterward in future (after all, the hybrid architecture
will continue in x86). And I think, since socket/core/thread are the three
default QEMU topology hierarchies, I understand that it would be best for
thread to always have core as parent.
[PULL 03/49] hw: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
[PULL 07/49] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit, Philippe Mathieu-Daudé, 2025/01/12
[PULL 06/49] hw/usb: Inline usb_new(), Philippe Mathieu-Daudé, 2025/01/12
[PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented), Philippe Mathieu-Daudé, 2025/01/12
[PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
[PULL 10/49] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
[PULL 11/49] hw/net/xilinx_ethlite: Access TX_GIE register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 12/49] hw/net/xilinx_ethlite: Access TX_LEN register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 13/49] hw/net/xilinx_ethlite: Access TX_CTRL register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 14/49] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12