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[PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) |
Date: |
Sun, 12 Jan 2025 23:16:44 +0100 |
Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
00000000810007f4-0000000081001fff (prio 0, i/o): xlnx.xps-ethernetlite
@00000000000007f4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-7-philmd@linaro.org>
---
hw/net/xilinx_ethlite.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 88ab331acce..442467abeb8 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -28,15 +28,18 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qom/object.h"
+#include "qapi/error.h"
#include "exec/tswap.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
#include "net/net.h"
#include "trace.h"
#define R_TX_BUF0 0
#define BUFSZ_MAX 0x07e4
+#define A_MDIO_BASE 0x07e4
#define R_TX_LEN0 (0x07f4 / 4)
#define R_TX_GIE0 (0x07f8 / 4)
#define R_TX_CTRL0 (0x07fc / 4)
@@ -72,6 +75,7 @@ struct XlnxXpsEthLite
uint32_t c_rx_pingpong;
unsigned int port_index; /* dual port RAM index */
+ UnimplementedDeviceState mdio;
uint32_t regs[R_MAX];
};
@@ -232,6 +236,14 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error
**errp)
{
XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
+ object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
+ qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
+ memory_region_add_subregion(&s->mmio, A_MDIO_BASE,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio),
0));
+
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id,
--
2.47.1
- [PULL 00/49] Misc HW patches for 2025-01-12, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 01/49] pc-bios/meson.build: Silent unuseful DTC warnings, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 02/49] target: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 05/49] hw/usb: Inline usb_try_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 04/49] hw: Add QOM parentship relation with CPUs, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 03/49] hw: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 07/49] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 06/49] hw/usb: Inline usb_new(), Philippe Mathieu-Daudé, 2025/01/12
- [PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented),
Philippe Mathieu-Daudé <=
- [PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 10/49] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 11/49] hw/net/xilinx_ethlite: Access TX_GIE register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 12/49] hw/net/xilinx_ethlite: Access TX_LEN register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 13/49] hw/net/xilinx_ethlite: Access TX_CTRL register for each port, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 14/49] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 15/49] hw/net/xilinx_ethlite: Map TX_LEN as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 16/49] hw/net/xilinx_ethlite: Map TX_GIE as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 17/49] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12
- [PULL 18/49] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region, Philippe Mathieu-Daudé, 2025/01/12