[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 04/49] hw: Add QOM parentship relation with CPUs
From: |
Zhao Liu |
Subject: |
Re: [PULL 04/49] hw: Add QOM parentship relation with CPUs |
Date: |
Wed, 15 Jan 2025 22:07:22 +0800 |
> > I remember that this was your idea all along, and I'm not sure if you're
> > also referring to my previous patches about hybrid topology :-), which I'll
>
> I'm sorry, I've should've reviewed it long time ago.
> But it got lost in from my review queue, can you give me a pointer
> to the latest you've posted, please?
You are very kind, no need sorry :-). I have also been inspired by many
of your previous ideas (although my work may not fully meet your
expectations yet). Here are the links:
[1]: qom-topo series, which tries to abstract every topology levels as
devices and build a topology tree:
https://lore.kernel.org/qemu-devel/20240919015533.766754-1-zhao1.liu@intel.com/
[2]: hybird-topo series, based on [1], which allows i386 to customize
topology tree:
https://lore.kernel.org/qemu-devel/20240919061128.769139-1-zhao1.liu@intel.com/
Thanks,
Zhao
- [PULL 02/49] target: Replace DEVICE(object_new) -> qdev_new(), (continued)
[PULL 03/49] hw: Replace DEVICE(object_new) -> qdev_new(), Philippe Mathieu-Daudé, 2025/01/12
[PULL 07/49] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit, Philippe Mathieu-Daudé, 2025/01/12
[PULL 06/49] hw/usb: Inline usb_new(), Philippe Mathieu-Daudé, 2025/01/12
[PULL 08/49] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented), Philippe Mathieu-Daudé, 2025/01/12
[PULL 09/49] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
[PULL 10/49] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper, Philippe Mathieu-Daudé, 2025/01/12
[PULL 11/49] hw/net/xilinx_ethlite: Access TX_GIE register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 12/49] hw/net/xilinx_ethlite: Access TX_LEN register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 13/49] hw/net/xilinx_ethlite: Access TX_CTRL register for each port, Philippe Mathieu-Daudé, 2025/01/12
[PULL 14/49] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO, Philippe Mathieu-Daudé, 2025/01/12