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[PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile(
From: |
Alistair Francis |
Subject: |
[PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() |
Date: |
Fri, 8 Mar 2024 21:11:25 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.
Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu' in this case.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index dd5228c288..ee4c349972 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1075,6 +1075,7 @@ static void cpu_set_profile(Object *obj, Visitor *v,
const char *name,
#ifndef CONFIG_USER_ONLY
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
+ object_property_set_bool(obj, "mmu", true, NULL);
const char *satp_prop = satp_mode_str(profile->satp_mode,
riscv_cpu_is_32bit(cpu));
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
--
2.44.0
- [PULL 00/34] riscv-to-apply queue, Alistair Francis, 2024/03/08
- [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location, Alistair Francis, 2024/03/08
- [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table, Alistair Francis, 2024/03/08
- [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt(), Alistair Francis, 2024/03/08
- [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe, Alistair Francis, 2024/03/08
- [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile(),
Alistair Francis <=
- [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux, Alistair Francis, 2024/03/08
- [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM, Alistair Francis, 2024/03/08
- [PULL 08/34] target/riscv: add riscv,isa to named features, Alistair Francis, 2024/03/08
- [PULL 09/34] target/riscv: add remaining named features, Alistair Francis, 2024/03/08
- [PULL 10/34] target/riscv: Reset henvcfg to zero, Alistair Francis, 2024/03/08
- [PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating, Alistair Francis, 2024/03/08
- [PULL 12/34] target/riscv: Promote svade to a normal extension, Alistair Francis, 2024/03/08