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[PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt(
From: |
Alistair Francis |
Subject: |
[PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt() |
Date: |
Fri, 8 Mar 2024 21:11:19 +1000 |
From: Jason Chien <jason.chien@sifive.com>
The original implementation sets $pc to the address read from the jump
vector table first and links $ra with the address of the next instruction
after the updated $pc. After jumping to the updated $pc and executing the
next ret instruction, the program jumps to $ra, which is in the same
function currently executing, which results in an infinite loop.
This commit stores the jump address in a temporary, updates $ra with the
current $pc, and copies the temporary to $pc.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240207081820.28559-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc
b/target/riscv/insn_trans/trans_rvzce.c.inc
index 2d992e14c4..cd234ad960 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -293,12 +293,14 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt
*a)
{
REQUIRE_ZCMT(ctx);
+ TCGv addr = tcg_temp_new();
+
/*
* Update pc to current for the non-unwinding exception
* that might come from cpu_ld*_code() in the helper.
*/
gen_update_pc(ctx, 0);
- gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
+ gen_helper_cm_jalt(addr, tcg_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
@@ -307,6 +309,8 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
gen_set_gpr(ctx, xRA, succ_pc);
}
+ tcg_gen_mov_tl(cpu_pc, addr);
+
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return true;
--
2.44.0
- [PULL 00/34] riscv-to-apply queue, Alistair Francis, 2024/03/08
- [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location, Alistair Francis, 2024/03/08
- [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table, Alistair Francis, 2024/03/08
- [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt(),
Alistair Francis <=
- [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe, Alistair Francis, 2024/03/08
- [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile(), Alistair Francis, 2024/03/08
- [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux, Alistair Francis, 2024/03/08
- [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM, Alistair Francis, 2024/03/08
- [PULL 08/34] target/riscv: add riscv,isa to named features, Alistair Francis, 2024/03/08
- [PULL 09/34] target/riscv: add remaining named features, Alistair Francis, 2024/03/08
- [PULL 10/34] target/riscv: Reset henvcfg to zero, Alistair Francis, 2024/03/08