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[PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table
From: |
Alistair Francis |
Subject: |
[PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table |
Date: |
Fri, 8 Mar 2024 21:11:21 +1000 |
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index fb8baf64f6..0baa902fea 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -174,6 +174,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry
*uart_memmap,
aml_append(scope, dev);
}
+/*
+ * Serial Port Console Redirection Table (SPCR)
+ * Rev: 1.07
+ */
+
+static void
+spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
+{
+ AcpiSpcrData serial = {
+ .interface_type = 0, /* 16550 compatible */
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
+ .base_addr.width = 32,
+ .base_addr.offset = 0,
+ .base_addr.size = 1,
+ .base_addr.addr = s->memmap[VIRT_UART0].base,
+ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
+ .pc_interrupt = 0,
+ .interrupt = UART0_IRQ,
+ .baud_rate = 7, /* 15200 */
+ .parity = 0,
+ .stop_bits = 1,
+ .flow_control = 0,
+ .terminal_type = 3, /* ANSI */
+ .language = 0, /* Language */
+ .pci_device_id = 0xffff, /* not a PCI device*/
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
+ .pci_bus = 0,
+ .pci_device = 0,
+ .pci_function = 0,
+ .pci_flags = 0,
+ .pci_segment = 0,
+ };
+
+ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -555,6 +591,9 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s);
+ acpi_add_table(table_offsets, tables_blob);
+ spcr_setup(tables_blob, tables->linker, s);
+
acpi_add_table(table_offsets, tables_blob);
{
AcpiMcfgInfo mcfg = {
--
2.44.0
- [PULL 00/34] riscv-to-apply queue, Alistair Francis, 2024/03/08
- [PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location, Alistair Francis, 2024/03/08
- [PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table,
Alistair Francis <=
- [PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt(), Alistair Francis, 2024/03/08
- [PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe, Alistair Francis, 2024/03/08
- [PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile(), Alistair Francis, 2024/03/08
- [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux, Alistair Francis, 2024/03/08
- [PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM, Alistair Francis, 2024/03/08
- [PULL 08/34] target/riscv: add riscv,isa to named features, Alistair Francis, 2024/03/08
- [PULL 09/34] target/riscv: add remaining named features, Alistair Francis, 2024/03/08