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[PULL v1 11/14] target/microblaze: Fix FPU2 instruction check
From: |
Edgar E. Iglesias |
Subject: |
[PULL v1 11/14] target/microblaze: Fix FPU2 instruction check |
Date: |
Thu, 14 May 2020 16:13:59 +0200 |
From: Joe Komlodi <address@hidden>
The check to see if we can use FPU2 instructions would return 0 if
cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK.
This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used.
Signed-off-by: Joe Komlodi <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 92b3630804..8079724f32 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1392,7 +1392,7 @@ static int dec_check_fpuv2(DisasContext *dc)
tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
- return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
+ return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
}
static void dec_fpu(DisasContext *dc)
--
2.20.1
- [PULL v1 01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg, (continued)
- [PULL v1 01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg, Edgar E. Iglesias, 2020/05/14
- [PULL v1 02/14] hw/net/xilinx_axienet: Cleanup stream->push assignment, Edgar E. Iglesias, 2020/05/14
- [PULL v1 03/14] hw/net/xilinx_axienet: Remove unncessary cast, Edgar E. Iglesias, 2020/05/14
- [PULL v1 05/14] hw/core: stream: Add an end-of-packet flag, Edgar E. Iglesias, 2020/05/14
- [PULL v1 06/14] hw/net/xilinx_axienet: Handle fragmented packets from DMA, Edgar E. Iglesias, 2020/05/14
- [PULL v1 04/14] hw/dma/xilinx_axidma: Add DMA memory-region property, Edgar E. Iglesias, 2020/05/14
- [PULL v1 07/14] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor, Edgar E. Iglesias, 2020/05/14
- [PULL v1 08/14] hw/dma/xilinx_axidma: s2mm: Support stream fragments, Edgar E. Iglesias, 2020/05/14
- [PULL v1 09/14] MAINTAINERS: Add myself as streams maintainer, Edgar E. Iglesias, 2020/05/14
- [PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation, Edgar E. Iglesias, 2020/05/14
- [PULL v1 11/14] target/microblaze: Fix FPU2 instruction check,
Edgar E. Iglesias <=
- [PULL v1 12/14] target/microblaze: gdb: Extend the number of registers presented to GDB, Edgar E. Iglesias, 2020/05/14
- [PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting, Edgar E. Iglesias, 2020/05/14
- [PULL v1 14/14] target/microblaze: monitor: Increase the number of registers reported, Edgar E. Iglesias, 2020/05/14
- Re: [PULL v1 00/14] Xilinx queue 2020-05-14, Peter Maydell, 2020/05/14