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[PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting
From: |
Edgar E. Iglesias |
Subject: |
[PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting |
Date: |
Thu, 14 May 2020 16:14:01 +0200 |
From: Joe Komlodi <address@hidden>
SRegs used to be reported to GDB by iterating over the SRegs array,
however we do not store them in an order that allows them to be
reported to GDB in that way.
To fix this, a simple map is used to map the register GDB wants to its
location in the SRegs array.
Signed-off-by: Joe Komlodi <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/gdbstub.c | 59 ++++++++++++++++++++++++++++++-------
1 file changed, 49 insertions(+), 10 deletions(-)
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 54cc7857d1..73e8973597 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -25,6 +25,21 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray
*mem_buf, int n)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
+ /*
+ * GDB expects SREGs in the following order:
+ * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
+ * They aren't stored in this order, so make a map.
+ * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
+ * map them to anything and return a value of 0 instead.
+ */
+ static const uint8_t sreg_map[6] = {
+ SR_PC,
+ SR_MSR,
+ SR_EAR,
+ SR_ESR,
+ SR_FSR,
+ SR_BTR
+ };
/*
* GDB expects registers to be reported in this order:
@@ -40,15 +55,16 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray
*mem_buf, int n)
n -= 32;
switch (n) {
case 0 ... 5:
- return gdb_get_reg32(mem_buf, env->sregs[n]);
+ return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]);
/* PVR12 is intentionally skipped */
case 6 ... 17:
n -= 6;
return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
- case 18 ... 24:
- /* Add an offset of 6 to resume where we left off with SRegs */
- n = n - 18 + 6;
- return gdb_get_reg32(mem_buf, env->sregs[n]);
+ case 18:
+ return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]);
+ /* Other SRegs aren't modeled, so report a value of 0 */
+ case 19 ... 24:
+ return gdb_get_reg32(mem_buf, 0);
case 25:
return gdb_get_reg32(mem_buf, env->slr);
case 26:
@@ -66,29 +82,52 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
CPUMBState *env = &cpu->env;
uint32_t tmp;
+ /*
+ * GDB expects SREGs in the following order:
+ * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
+ * They aren't stored in this order, so make a map.
+ * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
+ * map them to anything.
+ */
+ static const uint8_t sreg_map[6] = {
+ SR_PC,
+ SR_MSR,
+ SR_EAR,
+ SR_ESR,
+ SR_FSR,
+ SR_BTR
+ };
+
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
+ /*
+ * GDB expects registers to be reported in this order:
+ * R0-R31
+ * PC-BTR
+ * PVR0-PVR11
+ * EDR-TLBHI
+ * SLR-SHR
+ */
if (n < 32) {
env->regs[n] = tmp;
} else {
n -= 32;
switch (n) {
case 0 ... 5:
- env->sregs[n] = tmp;
+ env->sregs[sreg_map[n]] = tmp;
break;
/* PVR12 is intentionally skipped */
case 6 ... 17:
n -= 6;
env->pvr.regs[n] = tmp;
break;
- case 18 ... 24:
- /* Add an offset of 6 to resume where we left off with SRegs */
- n = n - 18 + 6;
- env->sregs[n] = tmp;
+ /* Only EDR is modeled in these indeces, so ignore the rest */
+ case 18:
+ env->sregs[SR_EDR] = tmp;
break;
case 25:
env->slr = tmp;
--
2.20.1
- [PULL v1 03/14] hw/net/xilinx_axienet: Remove unncessary cast, (continued)
- [PULL v1 03/14] hw/net/xilinx_axienet: Remove unncessary cast, Edgar E. Iglesias, 2020/05/14
- [PULL v1 05/14] hw/core: stream: Add an end-of-packet flag, Edgar E. Iglesias, 2020/05/14
- [PULL v1 06/14] hw/net/xilinx_axienet: Handle fragmented packets from DMA, Edgar E. Iglesias, 2020/05/14
- [PULL v1 04/14] hw/dma/xilinx_axidma: Add DMA memory-region property, Edgar E. Iglesias, 2020/05/14
- [PULL v1 07/14] hw/dma/xilinx_axidma: mm2s: Stream descriptor by descriptor, Edgar E. Iglesias, 2020/05/14
- [PULL v1 08/14] hw/dma/xilinx_axidma: s2mm: Support stream fragments, Edgar E. Iglesias, 2020/05/14
- [PULL v1 09/14] MAINTAINERS: Add myself as streams maintainer, Edgar E. Iglesias, 2020/05/14
- [PULL v1 10/14] target/microblaze: Add MFS Rd,EDR translation, Edgar E. Iglesias, 2020/05/14
- [PULL v1 11/14] target/microblaze: Fix FPU2 instruction check, Edgar E. Iglesias, 2020/05/14
- [PULL v1 12/14] target/microblaze: gdb: Extend the number of registers presented to GDB, Edgar E. Iglesias, 2020/05/14
- [PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting,
Edgar E. Iglesias <=
- [PULL v1 14/14] target/microblaze: monitor: Increase the number of registers reported, Edgar E. Iglesias, 2020/05/14
- Re: [PULL v1 00/14] Xilinx queue 2020-05-14, Peter Maydell, 2020/05/14