Re: [PATCH 39/71] target/arm: Add SVL to TB flags

[Peter Maydell]

On Thu, 2 Jun 2022 at 23:18, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We need SVL separate from VL for RDSVL at al, as well as

"et al"

> ZA storage loads and stores, which do not require PSTATE.SM.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h           | 12 ++++++++++++
>  target/arm/translate.h     |  1 +
>  target/arm/helper.c        |  8 +++++++-
>  target/arm/translate-a64.c |  1 +
>  4 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e41a75a3a3..0c32c3afaa 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
>  FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
>  FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
>  FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
> +FIELD(TBFLAG_A64, SVL, 24, 4)

Given that both SVE and SME start with an 'S', maybe
"SME_VL" would be less prone to confusion? On the other hand,
SVL is the architectural name, so maybe that's best.

>  /*
>   * Helpers for using the above.
> @@ -3337,6 +3338,17 @@ static inline int sve_vq_cached(CPUARMState *env)
>      return EX_TBFLAG_A64(env->hflags, VL) + 1;
>  }
>
> +/**
> + * sme_vq_cached
> + * @env: the cpu context
> + *
> + * Return the SVL cached within env->hflags, in units of quadwords.
> + */
> +static inline int sme_vq_cached(CPUARMState *env)

Same remark as earlier about not needing to put "cached" in the function name.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM