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Re: [PATCH 38/71] target/arm: Introduce sve_vqm1_for_el_sm
From: |
Peter Maydell |
Subject: |
Re: [PATCH 38/71] target/arm: Introduce sve_vqm1_for_el_sm |
Date: |
Tue, 7 Jun 2022 10:54:27 +0100 |
On Thu, 2 Jun 2022 at 23:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When Streaming SVE mode is enabled, the size is taken from
> SMCR_ELx instead of ZCR_ELx. The format is shared, but the
> set of vector lengths is not. Further, Streaming SVE does
> not require any particular length to be supported.
>
> Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM
> to the new function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH 36/71] target/arm: Unexport aarch64_add_*_properties, (continued)
- [PATCH 36/71] target/arm: Unexport aarch64_add_*_properties, Richard Henderson, 2022/06/02
- [PATCH 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len, Richard Henderson, 2022/06/02
- [PATCH 39/71] target/arm: Add SVL to TB flags, Richard Henderson, 2022/06/02
- [PATCH 26/71] target/arm: Add SMCR_ELx, Richard Henderson, 2022/06/02
- [PATCH 38/71] target/arm: Introduce sve_vqm1_for_el_sm, Richard Henderson, 2022/06/02
- Re: [PATCH 38/71] target/arm: Introduce sve_vqm1_for_el_sm,
Peter Maydell <=
- [PATCH 37/71] target/arm: Add cpu properties for SME, Richard Henderson, 2022/06/02
- [PATCH 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h, Richard Henderson, 2022/06/02
- [PATCH 42/71] target/arm: Trap AdvSIMD usage when Streaming SVE is active, Richard Henderson, 2022/06/02
- [PATCH 41/71] target/arm: Add infrastructure for disas_sme, Richard Henderson, 2022/06/02
- [PATCH 43/71] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL, Richard Henderson, 2022/06/02