Re: issues with technology editing in version 7

The reason I reverted to using version 7 is because I ran into issues converting a technology to a library for editing in version 8.4. Below is a response from Steve Rubin when I first reported this problem. So far, version 7 has been behaving fairly well - an occasional crash but I've been careful about backing up libraries.

At 10:40 PM 4/1/2007, you wrote:

I'm using version 8.4.

Pierce

Steven Rubin <address@hidden> wrote:

At 12:47 AM 4/1/2007, you wrote:

>Hello,

>

>I think I have found what seems to be a bug. I am trying to add a

>pbase layer and then an npn transistor node to the mocmos

>technology. I have tried a simple experiment where I converted a

>technology to library for editing, and chose mocmos. Then I tried to

>immediately convert the library back to a technology, giving it the

>name: mocmos_abn. This failed, with Electric having a problem with

>determining the stretching rules for the metal-1 pin layer. At other

>times, the problem can be with the node-P-Transistor-Scalable. I've

>tried several things and Electric always finds a problem with things

>I haven't touched, which is why this really seems like a bug to me.

I think this has been fixed since 8.4 was released. However, it is not a simple fix...you would need a completely new release.

We plan to make one in less than 2 months, but that may be a long wait for you.

Alternatively, you could hand-edit the technology library to make it more useful. Nodes are described with 4 separate examples plus some text. Each of these 5 pieces of graphical information must be far enough from the others that they can be easily separated. The error message that you are getting indicates they are too close. So you could hand-edit these cells to move them farther apart.

-Steve

address@hidden wrote:

I've since found that the metal spacing error mentioned below does get detected by the DRC. I've also discovered that connecting to the transistor pins is better than I first thought, if I work with it, but I still haven't been able to avoid OVERLAP DRC errors.

Pierce

Pierce Keating <address@hidden> wrote:

I have have been attempting to modify the mocmos library for the (MOSIS) AMI 1.5u SCNA ABN process. In the modified technology, I built an NPN transistor using a pbase layer, all created according to the SCNA layer map as described here: http://www.mosis.com/Technical/Layermaps/lm-scmos_scna.html

(I also removed the P-Well in the N-Transistor, since this process does not have a P-Well.)

There are at least two issues I have run into. First I deliberately included a metal1-metal1 spacing error to see if the DRC would detect the error but it doesn't. Also, I can't seem to connect to the pins of the npn transistor Node, when trying to use the node in a layout. Actually I can connect to them but not without a DRC metal1 spacing error. For other nodes, the layout editor seems to know to connect a metal1 arc to a metal1 port, and without DRC errors.

I've attached the libary to this email. If anyone would check it out and let me know what I'm doing wrong I would appreciate it very much.

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From:	Pierce Keating
Subject:	Re: issues with technology editing in version 7
Date:	Sun, 22 Apr 2007 10:44:24 -0700 (PDT)