I've since found that the metal spacing error mentioned below does get detected by the DRC. I've also discovered that connecting to the transistor pins is better than I first thought, if I work with it, but I still haven't been able to avoid OVERLAP DRC errors.
Hello,
I have have been attempting to modify the mocmos library for the (MOSIS) AMI 1.5u SCNA ABN process. In the modified technology, I built an NPN transistor using a pbase layer, all created according to the SCNA layer map as described here:
http://www.mosis.com/Technical/Layermaps/lm-scmos_scna.html
(I also removed the P-Well in the N-Transistor, since this process does not have a P-Well.)
There are at least two issues I have run into. First I deliberately included a metal1-metal1 spacing error to see if the DRC would detect the error but it doesn't. Also, I can't seem to connect to the pins of the npn transistor Node, when trying to use the node in a layout. Actually I can connect to them but not without a DRC metal1 spacing error. For other nodes, the layout editor seems to know to connect a metal1 arc to a metal1 port, and without DRC errors.
I've attached the libary to this email. If anyone would check it out and let me know what I'm doing wrong I would appreciate it very much.
Thank you,
Pierce
Keating
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