Is there a way to stop designated DRC errors? For example, when a Metal1-P Active connector is placed on a P transistor active region, a DRC error is generated:
DRC error 4 of 7: Spacing (layer P-Active): node Metal-1-P-Active-Con OVERLAPS arc P-Active [rule 2.2]
However I am merely connecting the transistor drain, so I would like to suppress this error.
Other times like layers might be intended to touch and a DRC error is correctly generated. However, I would often like to selectively suppress these errors as well. Is there a way to do this?
Thanks very much,
Pierce