Re: [PATCH v5 02/54] accel/tcg: Honor atomicity of loads

[Richard Henderson]

On 5/16/23 06:13, Peter Maydell wrote:
> On Mon, 15 May 2023 at 15:35, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > Create ldst_atomicity.c.inc.
> >
> > Not required for user-only code loads, because we've ensured that
> > the page is read-only before beginning to translate code.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> > v5: Dropped r-b because of MO_ATOM_* reorg
> > ---
>
> > +/**
> > + * load_atomic16:
> > + * @pv: host address
> > + *
> > + * Atomically load 16 aligned bytes from @pv.
> > + */
> > +static inline Int128 load_atomic16(void *pv)
> > +{
> > +#ifdef CONFIG_ATOMIC128
> > +    __uint128_t *p = __builtin_assume_aligned(pv, 16);
> > +    Int128Alias r;
> > +
> > +    r.u = qatomic_read__nocheck(p);
> > +    return r.s;
> > +#else
> > +    qemu_build_not_reached();
> > +#endif
> > +}
>
> Something that I remembered: Are we OK with this potentially barfing
> if you try it on read-only memory?

For system mode it is ok, but for user-only, no we are not ok with that.

I was not aware that clang was expanding this inline for aarch64 v8.0 -- I would have 
hoped it would be true only for LSE2.

Any thoughts for detecting this in configure/meson, or considering that I'm already doing 
some per-host ifdeffery simply rely on that entirely.  There are only 4 such hosts, after 
all, so it's not terribly difficult.


r~