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[PATCH v5 17/54] tcg/ppc: Use full load/store helpers in user-only mode
From: |
Richard Henderson |
Subject: |
[PATCH v5 17/54] tcg/ppc: Use full load/store helpers in user-only mode |
Date: |
Mon, 15 May 2023 07:32:36 -0700 |
Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 44 ----------------------------------------
1 file changed, 44 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 6a81916e64..218602c10c 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1962,7 +1962,6 @@ static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) +
1] = {
[MO_BSWAP | MO_UQ] = STDBRX,
};
-#if defined (CONFIG_SOFTMMU)
static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg)
{
if (arg < 0) {
@@ -2012,49 +2011,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_b(s, 0, lb->raddr);
return true;
}
-#else
-static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
-{
- if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
- return false;
- }
-
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- TCGReg arg = TCG_REG_R4;
-
- arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
- if (l->addrlo_reg != arg) {
- tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
- tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
- } else if (l->addrhi_reg != arg + 1) {
- tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
- tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg);
- tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1);
- tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0);
- }
- } else {
- tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg);
- }
- tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0);
-
- /* "Tail call" to the helper, with the return address back inline. */
- tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld
- : helper_unaligned_st));
- return true;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- return tcg_out_fail_alignment(s, l);
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- return tcg_out_fail_alignment(s, l);
-}
-#endif /* SOFTMMU */
typedef struct {
TCGReg base;
--
2.34.1
- Re: [PATCH v5 02/54] accel/tcg: Honor atomicity of loads, (continued)
- [PATCH v5 06/54] tcg/tci: Use helper_{ld,st}*_mmu for user-only, Richard Henderson, 2023/05/15
- [PATCH v5 05/54] accel/tcg: Implement helper_{ld, st}*_mmu for user-only, Richard Henderson, 2023/05/15
- [PATCH v5 08/54] meson: Detect atomic128 support with optimization, Richard Henderson, 2023/05/15
- [PATCH v5 03/54] accel/tcg: Honor atomicity of stores, Richard Henderson, 2023/05/15
- [PATCH v5 07/54] tcg: Add 128-bit guest memory primitives, Richard Henderson, 2023/05/15
- [PATCH v5 17/54] tcg/ppc: Use full load/store helpers in user-only mode,
Richard Henderson <=
- [PATCH v5 09/54] tcg/i386: Add have_atomic16, Richard Henderson, 2023/05/15
- [PATCH v5 12/54] tcg/aarch64: Detect have_lse, have_lse2 for linux, Richard Henderson, 2023/05/15
- [PATCH v5 11/54] accel/tcg: Add aarch64 specific support in ldst_atomicity, Richard Henderson, 2023/05/15
[PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin, Richard Henderson, 2023/05/15
[PATCH v5 19/54] tcg/riscv: Use full load/store helpers in user-only mode, Richard Henderson, 2023/05/15