Re: [PATCH v5 02/54] accel/tcg: Honor atomicity of loads

[Richard Henderson]

On 5/15/23 09:43, Peter Maydell wrote:
> > +static uint16_t load_atom_2(CPUArchState *env, uintptr_t ra,
> > +                            void *pv, MemOp memop)
> > +{
> > +    uintptr_t pi = (uintptr_t)pv;
> > +    int atmax;
> > +
> > +    if (likely((pi & 1) == 0)) {
> > +        return load_atomic2(pv);
> > +    }
> > +    if (HAVE_al16_fast) {
> > +        return load_atom_extract_al16_or_al8(pv, 2);
> > +    }
> > +
> > +    atmax = required_atomicity(env, pi, memop);
> > +    switch (atmax) {
> > +    case MO_8:
> > +        return lduw_he_p(pv);
> > +    case MO_16:
> > +        /* The only case remaining is MO_ATOM_WITHIN16. */
> > +        if (!HAVE_al8_fast && (pi & 3) == 1) {
> > +            /* Big or little endian, we want the middle two bytes. */
> > +            return load_atomic4(pv - 1) >> 8;
> > +        }
> > +        if (unlikely((pi & 15) != 7)) {
>
> Why is this the unlikely case ?

Ug, it's not.  Assuming random distribution of misalignment, this is 6 of 7 
cases.
I'll remove all markup, as it doesn't enhance understanding.


r~