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[Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes |
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Date: |
Sun, 18 Aug 2019 22:11:51 -0700 |
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 284f7a5..08db741 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -80,6 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
char ethclk_names[] = "pclk\0hclk\0tx_clk";
uint32_t plic_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle;
+ uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -98,6 +99,28 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+ hfclk_phandle = phandle++;
+ nodename = g_strdup_printf("/hfclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_HFCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
+ rtcclk_phandle = phandle++;
+ nodename = g_strdup_printf("/rtcclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_RTCCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/memory@%lx",
(long)memmap[SIFIVE_U_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 7a1a4f3..debbf28 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,6 +68,8 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
+ SIFIVE_U_HFCLK_FREQ = 33333333,
+ SIFIVE_U_RTCCLK_FREQ = 1000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
--
2.7.4
- [Qemu-riscv] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images, (continued)
- [Qemu-riscv] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes,
Bin Meng <=
- [Qemu-riscv] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/19