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[Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI reg
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size |
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Date: |
Sun, 18 Aug 2019 22:11:42 -0700 |
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
include/hw/riscv/sifive_e_prci.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index 603a54b..3afcb84 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -85,7 +85,7 @@ static void sifive_e_prci_init(Object *obj)
SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
- TYPE_SIFIVE_E_PRCI, 0x8000);
+ TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
index c4b76aa..698b0b4 100644
--- a/include/hw/riscv/sifive_e_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -47,6 +47,8 @@ enum {
SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
+#define SIFIVE_E_PRCI_REG_SIZE 0x1000
+
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
--
2.7.4
- [Qemu-riscv] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size,
Bin Meng <=
- [Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/19