[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "harti
|
From: |
Bin Meng |
|
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array |
|
Date: |
Fri, 23 Aug 2019 09:57:03 +0800 |
Hi Alistair,
On Fri, Aug 23, 2019 at 6:44 AM Alistair Francis <address@hidden> wrote:
>
> On Sun, Aug 18, 2019 at 10:27 PM Bin Meng <address@hidden> wrote:
> >
> > At present each hart's hartid in a RISC-V hart array is assigned
> > the same value of its index in the hart array. But for a system
> > that has multiple hart arrays, this is not the case any more.
> >
> > Add a new "hartid-base" property so that hartid number can be
> > assigned based on the property value.
> >
> > Signed-off-by: Bin Meng <address@hidden>
>
> Why do we need this patch?
>
Without this patch, we cannot create two clusters that represent 1 E51
(hartid 0) and 4 U54 (hart id 1-4). Current codes will create 1 E51
(hartid 0) and 4 U54 (hartid 0-3)
Regards,
Bin
- [Qemu-riscv] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header, (continued)
- [Qemu-riscv] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/19