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Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Referenc
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes |
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Date: |
Tue, 20 Aug 2019 11:26:55 -0700 |
On Sun, Aug 18, 2019 at 10:24 PM Bin Meng <address@hidden> wrote:
>
> Now that we have added a PRCI node, update existing UART and ethernet
> nodes to reference PRCI as their clock sources, to keep in sync with
> the Linux kernel device tree.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_u.c | 7 ++++---
> include/hw/riscv/sifive_u_prci.h | 10 ++++++++++
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index bd5551c..8818fd6 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -80,7 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> int cpu;
> uint32_t *cells;
> char *nodename;
> - char ethclk_names[] = "pclk\0hclk\0tx_clk";
> + char ethclk_names[] = "pclk\0hclk";
> uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
> uint32_t uartclk_phandle;
> uint32_t hfclk_phandle, rtcclk_phandle;
> @@ -265,7 +265,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> - ethclk_phandle, ethclk_phandle, ethclk_phandle);
> + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
> qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
> sizeof(ethclk_names));
> qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
> @@ -295,7 +295,8 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> 0x0, memmap[SIFIVE_U_UART0].base,
> 0x0, memmap[SIFIVE_U_UART0].size);
> - qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
>
> diff --git a/include/hw/riscv/sifive_u_prci.h
> b/include/hw/riscv/sifive_u_prci.h
> index 66eacb5..cdf1d33 100644
> --- a/include/hw/riscv/sifive_u_prci.h
> +++ b/include/hw/riscv/sifive_u_prci.h
> @@ -87,4 +87,14 @@ typedef struct SiFiveUPRCIState {
>
> DeviceState *sifive_u_prci_create(hwaddr addr);
>
> +/*
> + * Clock indexes for use by Device Tree data and the PRCI driver.
> + *
> + * These values are from sifive-fu540-prci.h in the Linux kernel.
> + */
> +#define PRCI_CLK_COREPLL 0
> +#define PRCI_CLK_DDRPLL 1
> +#define PRCI_CLK_GEMGXLPLL 2
> +#define PRCI_CLK_TLCLK 3
> +
> #endif /* HW_SIFIVE_U_PRCI_H */
> --
> 2.7.4
>
>
- [Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, (continued)
- [Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/19
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes,
Alistair Francis <=
- [Qemu-riscv] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/19
- [Qemu-riscv] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/19