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[PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore
From: |
Nicholas Piggin |
Subject: |
[PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore |
Date: |
Fri, 26 Jul 2024 09:52:52 +1000 |
This helps move core state from CPU to core structures.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv_core.c | 3 +++
include/hw/ppc/pnv_core.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index f40ab721d6..2da271ffb6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -278,6 +278,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
PowerPCCPU *cpu;
+ PnvCPUState *pnv_cpu;
obj = object_new(typename);
cpu = POWERPC_CPU(obj);
@@ -288,6 +289,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
object_property_add_child(OBJECT(pc), name, obj);
cpu->machine_data = g_new0(PnvCPUState, 1);
+ pnv_cpu = pnv_cpu_state(cpu);
+ pnv_cpu->pnv_core = pc;
object_unref(obj);
}
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index c6d62fd145..29cab9dfd9 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -54,6 +54,7 @@ struct PnvCoreClass {
#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
typedef struct PnvCPUState {
+ PnvCore *pnv_core;
Object *intc;
} PnvCPUState;
--
2.45.2
- [PULL 11/96] target/ppc/cpu_init: Synchronize HASHKEYR with KVM for migration, (continued)
- [PULL 11/96] target/ppc/cpu_init: Synchronize HASHKEYR with KVM for migration, Nicholas Piggin, 2024/07/25
- [PULL 12/96] target/ppc/cpu_init: Synchronize HASHPKEYR with KVM for migration, Nicholas Piggin, 2024/07/25
- [PULL 13/96] ppc/pnv: Update Power10's cfam id to use Power10 DD2, Nicholas Piggin, 2024/07/25
- [PULL 14/96] ppc/pnv: Fix loss of LPC SERIRQ interrupts, Nicholas Piggin, 2024/07/25
- [PULL 15/96] ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function, Nicholas Piggin, 2024/07/25
- [PULL 18/96] target/ppc: Fix msgsnd for POWER8, Nicholas Piggin, 2024/07/25
- [PULL 17/96] ppc/pnv: Implement ADU access to LPC space, Nicholas Piggin, 2024/07/25
- [PULL 16/96] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10, Nicholas Piggin, 2024/07/25
- [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore,
Nicholas Piggin <=
- [PULL 20/96] ppc/pnv: Move timebase state into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 21/96] target/ppc: Move SPR indirect registers into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines, Nicholas Piggin, 2024/07/25
- [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/25
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/25
- [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/25
- [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/25
- [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/25
- [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/25
- [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/25