[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for diffe
From: |
Nicholas Piggin |
Subject: |
[PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines |
Date: |
Fri, 26 Jul 2024 09:52:55 +1000 |
Use a class attribute to specify the number of SMT threads per core
permitted for different machines, 8 for powernv8 and 4 for powernv9/10.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 12 +++++++++---
include/hw/ppc/pnv.h | 1 +
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 91ff1be21f..a84e0e0e30 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -899,6 +899,7 @@ static void pnv_init(MachineState *machine)
PnvMachineState *pnv = PNV_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
+ int max_smt_threads = pmc->max_smt_threads;
char *fw_filename;
long fw_size;
uint64_t chip_ram_start = 0;
@@ -997,17 +998,19 @@ static void pnv_init(MachineState *machine)
pnv->num_chips =
machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
- if (machine->smp.threads > 8) {
- error_report("Cannot support more than 8 threads/core "
- "on a powernv machine");
+ if (machine->smp.threads > max_smt_threads) {
+ error_report("Cannot support more than %d threads/core "
+ "on %s machine", max_smt_threads, mc->desc);
exit(1);
}
+
if (!is_power_of_2(machine->smp.threads)) {
error_report("Cannot support %d threads/core on a powernv"
"machine because it must be a power of 2",
machine->smp.threads);
exit(1);
}
+
/*
* TODO: should we decide on how many chips we can create based
* on #cores and Venice vs. Murano vs. Naples chip type etc...,
@@ -2490,6 +2493,7 @@ static void pnv_machine_power8_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 8;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
@@ -2514,6 +2518,7 @@ static void pnv_machine_power9_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 4;
pmc->dt_power_mgt = pnv_dt_power_mgt;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
@@ -2538,6 +2543,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 4;
pmc->dt_power_mgt = pnv_dt_power_mgt;
xfc->match_nvt = pnv10_xive_match_nvt;
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 476b136146..1993dededf 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -76,6 +76,7 @@ struct PnvMachineClass {
/*< public >*/
const char *compat;
int compat_size;
+ int max_smt_threads;
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
void (*i2c_init)(PnvMachineState *pnv);
--
2.45.2
- [PULL 14/96] ppc/pnv: Fix loss of LPC SERIRQ interrupts, (continued)
- [PULL 14/96] ppc/pnv: Fix loss of LPC SERIRQ interrupts, Nicholas Piggin, 2024/07/25
- [PULL 15/96] ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function, Nicholas Piggin, 2024/07/25
- [PULL 18/96] target/ppc: Fix msgsnd for POWER8, Nicholas Piggin, 2024/07/25
- [PULL 17/96] ppc/pnv: Implement ADU access to LPC space, Nicholas Piggin, 2024/07/25
- [PULL 16/96] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10, Nicholas Piggin, 2024/07/25
- [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 20/96] ppc/pnv: Move timebase state into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 21/96] target/ppc: Move SPR indirect registers into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines,
Nicholas Piggin <=
- [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/25
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/25
- [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/25
- [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/25
- [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/25
- [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/25
- [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/25
- [PULL 30/96] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/25
- [PULL 31/96] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/25
- [PULL 32/96] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/25