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[PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10
From: |
Nicholas Piggin |
Subject: |
[PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10 |
Date: |
Fri, 26 Jul 2024 09:53:02 +1000 |
Power9/10 CPUs have PVR[51] set in small-core mode and clear in big-core
mode. This is used by skiboot firmware.
PVR is not hypervisor-privileged but it is not so important that spapr
to implement this because it's generally masked out of PVR matching code
in kernels, and only used by firmware.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv_core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 6dc05534d7..43cfeaa2d4 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -58,6 +58,10 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
env->nip = 0x10;
env->msr |= MSR_HVB; /* Hypervisor mode */
env->spr[SPR_HRMOR] = pc->hrmor;
+ if (pc->big_core) {
+ /* Clear "small core" bit on Power9/10 (this is set in default PVR) */
+ env->spr[SPR_PVR] &= ~PPC_BIT(51);
+ }
hreg_compute_hflags(env);
ppc_maybe_interrupt(env);
--
2.45.2
- [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore, (continued)
- [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 20/96] ppc/pnv: Move timebase state into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 21/96] target/ppc: Move SPR indirect registers into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 22/96] ppc/pnv: use class attribute to limit SMT threads for different machines, Nicholas Piggin, 2024/07/25
- [PULL 23/96] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/25
- [PULL 24/96] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/25
- [PULL 25/96] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/25
- [PULL 26/96] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/25
- [PULL 27/96] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/25
- [PULL 28/96] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/25
- [PULL 29/96] ppc/pnv: Implement big-core PVR for Power9/10,
Nicholas Piggin <=
- [PULL 30/96] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/25
- [PULL 31/96] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/25
- [PULL 32/96] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/25
- [PULL 33/96] ppc/pnv: Add a CPU nmi and resume function, Nicholas Piggin, 2024/07/25
- [PULL 35/96] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/25
- [PULL 34/96] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/25
- [PULL 36/96] ppc/pnv: Remove ppc target dependency from pnv_xscom.h, Nicholas Piggin, 2024/07/25
- [PULL 37/96] hw/ssi: Add SPI model, Nicholas Piggin, 2024/07/25
- [PULL 38/96] hw/ssi: Extend SPI model, Nicholas Piggin, 2024/07/25