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[PULL 13/96] ppc/pnv: Update Power10's cfam id to use Power10 DD2
From: |
Nicholas Piggin |
Subject: |
[PULL 13/96] ppc/pnv: Update Power10's cfam id to use Power10 DD2 |
Date: |
Fri, 26 Jul 2024 09:52:46 +1000 |
From: Aditya Gupta <adityag@linux.ibm.com>
Power10 DD1.0 was dropped in:
commit 8f054d9ee825 ("ppc: Drop support for POWER9 and POWER10 DD1 chips")
Use the newer Power10 DD2 chips cfam id.
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 2 +-
tests/qtest/pnv-xscom.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6b41d1d2dd..13cebd6ab9 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2087,7 +2087,7 @@ static void pnv_chip_power10_class_init(ObjectClass
*klass, void *data)
PnvChipClass *k = PNV_CHIP_CLASS(klass);
static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2,
16};
- k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
+ k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */
k->cores_mask = POWER10_CORE_MASK;
k->chip_pir = pnv_chip_pir_p10;
k->intc_create = pnv_chip_power10_intc_create;
diff --git a/tests/qtest/pnv-xscom.h b/tests/qtest/pnv-xscom.h
index 6f62941744..5aa1701ea7 100644
--- a/tests/qtest/pnv-xscom.h
+++ b/tests/qtest/pnv-xscom.h
@@ -56,7 +56,7 @@ static const PnvChip pnv_chips[] = {
.chip_type = PNV_CHIP_POWER10,
.cpu_model = "POWER10",
.xscom_base = 0x000603fc00000000ull,
- .cfam_id = 0x120da04900008000ull,
+ .cfam_id = 0x220da04980000000ull,
.first_core = 0x0,
.num_i2c = 4,
},
--
2.45.2
- [PULL 03/96] spapr: Free stdout path, (continued)
- [PULL 03/96] spapr: Free stdout path, Nicholas Piggin, 2024/07/25
- [PULL 04/96] ppc/vof: Fix unaligned FDT property access, Nicholas Piggin, 2024/07/25
- [PULL 05/96] accel/kvm: Introduce kvm_create_and_park_vcpu() helper, Nicholas Piggin, 2024/07/25
- [PULL 06/96] cpu-common.c: export cpu_get_free_index to be reused later, Nicholas Piggin, 2024/07/25
- [PULL 07/96] target/ppc: handle vcpu hotplug failure gracefully, Nicholas Piggin, 2024/07/25
- [PULL 08/96] target/ppc/arch_dump: set prstatus pid to cpuid, Nicholas Piggin, 2024/07/25
- [PULL 09/96] linux-header: PPC: KVM: Update one-reg ids for DEXCR, HASHKEYR and HASHPKEYR, Nicholas Piggin, 2024/07/25
- [PULL 10/96] target/ppc/cpu_init: Synchronize DEXCR with KVM for migration, Nicholas Piggin, 2024/07/25
- [PULL 11/96] target/ppc/cpu_init: Synchronize HASHKEYR with KVM for migration, Nicholas Piggin, 2024/07/25
- [PULL 12/96] target/ppc/cpu_init: Synchronize HASHPKEYR with KVM for migration, Nicholas Piggin, 2024/07/25
- [PULL 13/96] ppc/pnv: Update Power10's cfam id to use Power10 DD2,
Nicholas Piggin <=
- [PULL 14/96] ppc/pnv: Fix loss of LPC SERIRQ interrupts, Nicholas Piggin, 2024/07/25
- [PULL 15/96] ppc/pnv: Implement POWER9 LPC PSI serirq outputs and auto-clear function, Nicholas Piggin, 2024/07/25
- [PULL 18/96] target/ppc: Fix msgsnd for POWER8, Nicholas Piggin, 2024/07/25
- [PULL 17/96] ppc/pnv: Implement ADU access to LPC space, Nicholas Piggin, 2024/07/25
- [PULL 16/96] ppc/pnv: Begin a more complete ADU LPC model for POWER9/10, Nicholas Piggin, 2024/07/25
- [PULL 19/96] ppc/pnv: Add pointer from PnvCPUState to PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 20/96] ppc/pnv: Move timebase state into PnvCore, Nicholas Piggin, 2024/07/25
- [PULL 21/96] target/ppc: Move SPR indirect registers into PnvCore, Nicholas Piggin, 2024/07/25