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[Qemu-ppc] [PULL 19/28] pnv_core: Allocate cpu thread objects individual
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 19/28] pnv_core: Allocate cpu thread objects individually |
Date: |
Mon, 18 Jun 2018 13:53:15 +1000 |
Currently, we allocate space for all the cpu objects within a single core
in one big block. This was copied from an older version of the spapr code
and requires some ugly pointer manipulation to extract the individual
objects.
This design was due to a misunderstanding of qemu lifetime conventions and
has already been changed in spapr (in 94ad93bd "spapr_cpu_core: instantiate
CPUs separately".
Make an equivalent change in pnv_core to get rid of the nasty pointer
arithmetic.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_core.c | 11 +++++------
include/hw/ppc/pnv_core.h | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0314881316..0b9508d94d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -121,9 +121,9 @@ static int get_cpus_node(void *fdt)
*/
static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
- CPUState *cs = CPU(DEVICE(pc->threads));
+ PowerPCCPU *cpu = pc->threads[0];
+ CPUState *cs = CPU(cpu);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 01f47c8037..1e40f01e98 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -151,7 +151,6 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
PnvCore *pc = PNV_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
const char *typename = pnv_core_cpu_typename(pc);
- size_t size = object_type_get_instance_size(typename);
Error *local_err = NULL;
void *obj;
int i, j;
@@ -165,11 +164,11 @@ static void pnv_core_realize(DeviceState *dev, Error
**errp)
return;
}
- pc->threads = g_malloc0(size * cc->nr_threads);
+ pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
- obj = pc->threads + i * size;
+ obj = object_new(typename);
- object_initialize(obj, size, typename);
+ pc->threads[i] = POWERPC_CPU(obj);
snprintf(name, sizeof(name), "thread[%d]", i);
object_property_add_child(OBJECT(pc), name, obj, &error_abort);
@@ -179,7 +178,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
for (j = 0; j < cc->nr_threads; j++) {
- obj = pc->threads + j * size;
+ obj = OBJECT(pc->threads[j]);
pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
if (local_err) {
@@ -194,7 +193,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
err:
while (--i >= 0) {
- obj = pc->threads + i * size;
+ obj = OBJECT(pc->threads[i]);
object_unparent(obj);
}
g_free(pc->threads);
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index e337af7a3a..447ae761f7 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -34,7 +34,7 @@ typedef struct PnvCore {
CPUCore parent_obj;
/*< public >*/
- void *threads;
+ PowerPCCPU **threads;
uint32_t pir;
MemoryRegion xscom_regs;
--
2.17.1
- [Qemu-ppc] [PULL 01/28] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache, (continued)
- [Qemu-ppc] [PULL 01/28] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 13/28] mos6522: only clear the shift register interrupt upon write, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 08/28] mac_newworld: wire up programmer switch to NMI handler, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 09/28] adb: fix read reg 3 byte ordering, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 26/28] ppc/pnv: introduce a pnv_chip_core_realize() routine, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 14/28] mos6522: remove additional interrupt flag filter from mos6522_update_irq(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 20/28] pnv: Clean up cpu realize path, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 15/28] mos6522: expose mos6522_update_irq() through MOS6522DeviceClass, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 16/28] sm501: Do not clear read only bits when writing registers, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 18/28] pnv: Fix some error handling cpu realize(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 19/28] pnv_core: Allocate cpu thread objects individually,
David Gibson <=
- [Qemu-ppc] [PULL 10/28] adb: add property to disable direct reg 3 writes, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 05/28] ppc: introduce Core99MachinesState for the mac99 machine, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 22/28] spapr_cpu_core: convert last snprintf() to g_strdup_printf(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 27/28] target/ppc, spapr: Move VPA information to machine_data, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 06/28] mac_newworld: add via machine option to control mac99 VIA/ADB configuration, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 24/28] spapr_cpu_core: add missing rollback on realization path, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 12/28] xics_kvm: fix a build break, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 23/28] spapr_cpu_core: fix potential leak in spapr_cpu_core_realize(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 21/28] pnv: Add cpu unrealize path, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 17/28] spapr: Clean up cpu realize/unrealize paths, David Gibson, 2018/06/17