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[Qemu-ppc] [PULL 18/28] pnv: Fix some error handling cpu realize()
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 18/28] pnv: Fix some error handling cpu realize() |
Date: |
Mon, 18 Jun 2018 13:53:14 +1000 |
In pnv_core_realize() we call two functions with an Error * parameter in
succession, which will go badly if they both cause errors. In fact, a
failure in either of them indicates a qemu internal error, so we can just
use &error_abort in both cases.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/pnv_core.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 13ad7d9e04..01f47c8037 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -172,12 +172,9 @@ static void pnv_core_realize(DeviceState *dev, Error
**errp)
object_initialize(obj, size, typename);
snprintf(name, sizeof(name), "thread[%d]", i);
- object_property_add_child(OBJECT(pc), name, obj, &local_err);
+ object_property_add_child(OBJECT(pc), name, obj, &error_abort);
object_property_add_alias(obj, "core-pir", OBJECT(pc),
- "pir", &local_err);
- if (local_err) {
- goto err;
- }
+ "pir", &error_abort);
object_unref(obj);
}
--
2.17.1
- [Qemu-ppc] [PULL 02/28] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default, (continued)
- [Qemu-ppc] [PULL 02/28] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 01/28] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 13/28] mos6522: only clear the shift register interrupt upon write, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 08/28] mac_newworld: wire up programmer switch to NMI handler, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 09/28] adb: fix read reg 3 byte ordering, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 26/28] ppc/pnv: introduce a pnv_chip_core_realize() routine, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 14/28] mos6522: remove additional interrupt flag filter from mos6522_update_irq(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 20/28] pnv: Clean up cpu realize path, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 15/28] mos6522: expose mos6522_update_irq() through MOS6522DeviceClass, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 16/28] sm501: Do not clear read only bits when writing registers, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 18/28] pnv: Fix some error handling cpu realize(),
David Gibson <=
- [Qemu-ppc] [PULL 19/28] pnv_core: Allocate cpu thread objects individually, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 10/28] adb: add property to disable direct reg 3 writes, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 05/28] ppc: introduce Core99MachinesState for the mac99 machine, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 22/28] spapr_cpu_core: convert last snprintf() to g_strdup_printf(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 27/28] target/ppc, spapr: Move VPA information to machine_data, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 06/28] mac_newworld: add via machine option to control mac99 VIA/ADB configuration, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 24/28] spapr_cpu_core: add missing rollback on realization path, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 12/28] xics_kvm: fix a build break, David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 23/28] spapr_cpu_core: fix potential leak in spapr_cpu_core_realize(), David Gibson, 2018/06/17
- [Qemu-ppc] [PULL 21/28] pnv: Add cpu unrealize path, David Gibson, 2018/06/17