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[Qemu-ppc] [PULL 18/26] ppc: Properly tag the translation cache based on
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode |
Date: |
Tue, 7 Jun 2016 20:48:05 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We used to always flush the TLB when changing relocation mode in
MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).
We don't anymore since we have split mmu_idx for instruction and data.
However, since we hard code the mmu_idx in the translated code, we
now need to also make sure MSR:IR and MSR:DR are part of the hflags
used to tag translated code, so that we use different translated
code for different MMU settings.
Darwin gets hurt by this problem.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 12af61c..104b690 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
- (1 << MSR_LE) | (1 << MSR_VSX);
+ (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
--
2.5.5
- [Qemu-ppc] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, (continued)
- [Qemu-ppc] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 22/26] ppc: POWER7 has lq/stq instructions and stq need to check ISA, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 16/26] macio: use DMA memory interface for non-block ATAPI transfers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode,
David Gibson <=
- [Qemu-ppc] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 01/26] target-ppc/fpu_helper: Fix efscmp* instructions handling, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 09/26] spapr: Increase hotpluggable memory slots to 256, David Gibson, 2016/06/07
- Re: [Qemu-ppc] [PULL 00/26] ppc-for-2.7 queue 20160607, Peter Maydell, 2016/06/07