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[Qemu-ppc] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bi
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors |
Date: |
Tue, 7 Jun 2016 20:48:06 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
The processor only uses some bits of the address and invalidates an
entire congruence class. Some OSes such as Darwin and HelenOS take
advantage of this and occasionally invalidate the entire TLB by just
doing a series of 64 consecutive tlbie for example.
Our code tries to be too smart here only invalidating a segment
congruence class (ie, allowing more address bits to be relevant
in the invalidation), this fails miserably on those OSes.
Instead don't bother, do like ppc64 and blow the whole tlb when tlbie
is executed.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/mmu_helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index f5c4e69..a5e3878 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1969,6 +1969,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
/* XXX: this case should be optimized,
* giving a mask to tlb_flush_page
*/
+ /* This is broken, some CPUs invalidate a whole congruence
+ * class on an even smaller subset of bits and some OSes take
+ * advantage of this. Just blow the whole thing away.
+ */
+#if 0
tlb_flush_page(cs, addr | (0x0 << 28));
tlb_flush_page(cs, addr | (0x1 << 28));
tlb_flush_page(cs, addr | (0x2 << 28));
@@ -1985,6 +1990,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
tlb_flush_page(cs, addr | (0xD << 28));
tlb_flush_page(cs, addr | (0xE << 28));
tlb_flush_page(cs, addr | (0xF << 28));
+#else
+ tlb_flush(cs, 1);
+#endif
break;
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
--
2.5.5
- [Qemu-ppc] [PULL 13/26] ppc: fix hrfid, tlbia and slbia privilege, (continued)
- [Qemu-ppc] [PULL 13/26] ppc: fix hrfid, tlbia and slbia privilege, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 15/26] target-ppc: fixup bitrot in mmu_helper.c debug statements, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 03/26] vmstate: Define VARRAY with VMS_ALLOC, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 10/26] spapr: Introduce pseries-2.7 machine type, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 22/26] ppc: POWER7 has lq/stq instructions and stq need to check ISA, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors,
David Gibson <=
- [Qemu-ppc] [PULL 16/26] macio: use DMA memory interface for non-block ATAPI transfers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 01/26] target-ppc/fpu_helper: Fix efscmp* instructions handling, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 09/26] spapr: Increase hotpluggable memory slots to 256, David Gibson, 2016/06/07
- Re: [Qemu-ppc] [PULL 00/26] ppc-for-2.7 queue 20160607, Peter Maydell, 2016/06/07