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[Qemu-ppc] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in p
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode |
Date: |
Tue, 7 Jun 2016 20:48:13 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
The architecture specifies that mtspr/mfspr on an unknown SPR number
should act as a nop in privileged mode.
I haven't removed the warning however as it can be useful for
diagnosing.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2ad4f4a..b689475 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4351,7 +4351,10 @@ static inline void gen_op_mfspr(DisasContext *ctx)
qemu_log("Trying to read invalid spr %d (0x%03x) at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
}
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ /* Only generate an exception in user space, otherwise this is a nop */
+ if (ctx->pr) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ }
}
}
@@ -4503,7 +4506,11 @@ static void gen_mtspr(DisasContext *ctx)
}
fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+
+ /* Only generate an exception in user space, otherwise this is a nop */
+ if (ctx->pr) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ }
}
}
--
2.5.5
- [Qemu-ppc] [PULL 11/26] ppc: Better figure out if processor has HV mode, (continued)
- [Qemu-ppc] [PULL 11/26] ppc: Better figure out if processor has HV mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 13/26] ppc: fix hrfid, tlbia and slbia privilege, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 15/26] target-ppc: fixup bitrot in mmu_helper.c debug statements, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 03/26] vmstate: Define VARRAY with VMS_ALLOC, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 10/26] spapr: Introduce pseries-2.7 machine type, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 25/26] ppc: Add missing slbfee. instruction on ppc64 BookS processors, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 24/26] ppc: Fix slbia decode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 02/26] kvm: API to obtain max supported mem slots, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 06/26] spapr_iommu: Add root memory region, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 22/26] ppc: POWER7 has lq/stq instructions and stq need to check ISA, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 26/26] ppc: Do not take exceptions on unknown SPRs in privileged mode,
David Gibson <=
- [Qemu-ppc] [PULL 19/26] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 16/26] macio: use DMA memory interface for non-block ATAPI transfers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 20/26] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 05/26] spapr_iommu: Migrate full state, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 18/26] ppc: Properly tag the translation cache based on MMU mode, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 21/26] ppc: POWER7 had ACOP and PID registers, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 01/26] target-ppc/fpu_helper: Fix efscmp* instructions handling, David Gibson, 2016/06/07
- [Qemu-ppc] [PULL 09/26] spapr: Increase hotpluggable memory slots to 256, David Gibson, 2016/06/07
- Re: [Qemu-ppc] [PULL 00/26] ppc-for-2.7 queue 20160607, Peter Maydell, 2016/06/07