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[PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
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From: |
Anton Blanchard |
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Subject: |
[PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS |
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Date: |
Sun, 26 Jan 2025 07:20:55 +0000 |
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 312d8b1b81..2741f8bd8e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2410,10 +2410,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr
*a)
}
/* OPFVF with WIDEN */
-#define GEN_OPFVF_WIDEN_TRANS(NAME) \
+#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opfvf_widen_check(s, a)) { \
+ if (CHECK(s, a)) { \
uint32_t data = 0; \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
@@ -2429,8 +2429,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
return false; \
}
-GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
@@ -2512,7 +2512,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
/* Vector Widening Floating-Point Multiply */
GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
@@ -2537,10 +2537,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
/* Vector Floating-Point Square-Root Instruction */
--
2.34.1
- [PATCH 02/12] target/riscv: handle vrgather mask and source overlap, (continued)
- [PATCH 02/12] target/riscv: handle vrgather mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap, Anton Blanchard, 2025/01/26
- [PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register, Anton Blanchard, 2025/01/26
- [PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS,
Anton Blanchard <=
- [PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite, Anton Blanchard, 2025/01/26