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[PATCH 02/12] target/riscv: handle vrgather mask and source overlap
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From: |
Anton Blanchard |
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Subject: |
[PATCH 02/12] target/riscv: handle vrgather mask and source overlap |
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Date: |
Sun, 26 Jan 2025 07:20:46 +0000 |
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 20b1cb127b..c66cd95bdb 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3453,7 +3453,9 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr
*a)
require_align(a->rs1, s->lmul) &&
require_align(a->rs2, s->lmul) &&
(a->rd != a->rs2 && a->rd != a->rs1) &&
- require_vm(a->vm, a->rd);
+ require_vm(a->vm, a->rd) &&
+ require_vm(a->vm, a->rs1) &&
+ require_vm(a->vm, a->rs2);
}
static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
@@ -3470,7 +3472,9 @@ static bool vrgatherei16_vv_check(DisasContext *s,
arg_rmrr *a)
a->rs1, 1 << MAX(emul, 0)) &&
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0),
a->rs2, 1 << MAX(s->lmul, 0)) &&
- require_vm(a->vm, a->rd);
+ require_vm(a->vm, a->rd) &&
+ require_vm(a->vm, a->rs1) &&
+ require_vm(a->vm, a->rs2);
}
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
@@ -3483,7 +3487,8 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr
*a)
require_align(a->rd, s->lmul) &&
require_align(a->rs2, s->lmul) &&
(a->rd != a->rs2) &&
- require_vm(a->vm, a->rd);
+ require_vm(a->vm, a->rd) &&
+ require_vm(a->vm, a->rs2);
}
/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
--
2.34.1
- [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases, Anton Blanchard, 2025/01/26
- [PATCH 02/12] target/riscv: handle vrgather mask and source overlap,
Anton Blanchard <=
- [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap, Anton Blanchard, 2025/01/26
- [PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register, Anton Blanchard, 2025/01/26
- [PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS, Anton Blanchard, 2025/01/26