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[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap
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From: |
Anton Blanchard |
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Subject: |
[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap |
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Date: |
Sun, 26 Jan 2025 07:20:54 +0000 |
for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap
because it would mean a register is read with two different SEW
settings.
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 2309d9abd0..312d8b1b81 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -549,7 +549,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int
vs1, int vs2, int vm)
{
return vext_check_ds(s, vd, vs1, vm) &&
require_vm(vm, vs2) &&
- require_align(vs2, s->lmul + 1);
+ require_align(vs2, s->lmul + 1) &&
+ !is_overlapped(vs2, 1 << MAX(s->lmul+1, 0), vs1, 1 << MAX(s->lmul,
0));
}
static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
--
2.34.1
- [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases, Anton Blanchard, 2025/01/26
- [PATCH 02/12] target/riscv: handle vrgather mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap,
Anton Blanchard <=
- [PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register, Anton Blanchard, 2025/01/26
- [PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS, Anton Blanchard, 2025/01/26
- [PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite, Anton Blanchard, 2025/01/26