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[PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap
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From: |
Anton Blanchard |
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Subject: |
[PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap |
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Date: |
Sun, 26 Jan 2025 07:20:48 +0000 |
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index bc2780497e..f5ba1c4280 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -403,6 +403,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs,
int vm)
static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
return vext_check_ss(s, vd, vs2, vm) &&
+ require_vm(vm, vs1) &&
require_align(vs1, s->lmul);
}
--
2.34.1
- [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases, Anton Blanchard, 2025/01/26
- [PATCH 02/12] target/riscv: handle vrgather mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap,
Anton Blanchard <=
- [PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap, Anton Blanchard, 2025/01/26
- [PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register, Anton Blanchard, 2025/01/26
- [PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap, Anton Blanchard, 2025/01/26
- [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS, Anton Blanchard, 2025/01/26
- [PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite, Anton Blanchard, 2025/01/26