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[PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro
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From: |
Alistair Francis |
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Subject: |
[PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro |
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Date: |
Tue, 4 May 2021 08:13:20 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 24 +++++++++++++++---------
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 3a0e79e545..d738e2fdbd 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -195,17 +195,6 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE SATP32_MODE
-#define HGATP_VMID SATP32_ASID
-#define HGATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE SATP64_MODE
-#define HGATP_VMID SATP64_ASID
-#define HGATP_PPN SATP64_PPN
-#endif
-
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1018c0036d..d9defbdd34 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
}
widened = 0;
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP64_MODE);
+ }
widened = 2;
}
/* status.SUM will be ignored if execute on background */
@@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
- int page_fault_exceptions;
+ int page_fault_exceptions, vm;
+
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->satp, SATP_MODE);
+ } else if (riscv_cpu_is_32bit(env)) {
+ vm = get_field(env->hgatp, SATP32_MODE);
} else {
- page_fault_exceptions =
- get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->hgatp, SATP64_MODE);
}
+ page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
--
2.31.1
- [PULL 26/42] target/riscv/pmp: Remove outdated comment, (continued)
- [PULL 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/03
- [PULL 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/03
- [PULL 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/03
- [PULL 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/03
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/03
- [PULL 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/03
- [PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/03
- [PULL 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/03
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/03
- [PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro,
Alistair Francis <=
- [PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/03
- [PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/03
- [PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/03
- [PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/03
- [PULL 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/03
- Re: [PULL 00/42] riscv-to-apply queue, Peter Maydell, 2021/05/05