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[PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd inst
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From: |
Alistair Francis |
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Subject: |
[PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions |
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Date: |
Tue, 4 May 2021 08:13:16 +1000 |
From: Frank Chang <frank.chang@sifive.com>
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In RISC-V Unprivileged ISA spec:
The fused multiply-add instructions must set the invalid
operation exception flag when the multiplicands are Inf and
zero, even when the addend is a quiet NaN.
This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
fpu/softfloat-specialize.c.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index 9ea318f3e2..78f699d6f8 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -627,6 +627,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
} else {
return 1;
}
+#elif defined(TARGET_RISCV)
+ /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 3; /* default NaN */
#elif defined(TARGET_XTENSA)
/*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
--
2.31.1
- [PULL 23/42] target/riscv: Add ePMP CSR access functions, (continued)
- [PULL 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/03
- [PULL 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/03
- [PULL 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/03
- [PULL 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/03
- [PULL 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/03
- [PULL 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/03
- [PULL 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/03
- [PULL 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/03
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/03
- [PULL 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/03
- [PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions,
Alistair Francis <=
- [PULL 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/03
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/03
- [PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/03
- [PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/03
- [PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/03
- [PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/03