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[PULL 21/42] target/riscv: Define ePMP mseccfg
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From: |
Alistair Francis |
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Subject: |
[PULL 21/42] target/riscv: Define ePMP mseccfg |
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Date: |
Tue, 4 May 2021 08:13:06 +1000 |
From: Hou Weiying <weiying_hou@outlook.com>
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
- Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77b4f..24d89939a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG 0x390
+#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
--
2.31.1
- [PULL 11/42] target/riscv: Fix 32-bit HS mode access permissions, (continued)
- [PULL 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/03
- [PULL 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/03
- [PULL 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/03
- [PULL 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/03
- [PULL 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/03
- [PULL 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/03
- [PULL 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/03
- [PULL 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/03
- [PULL 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/03
- [PULL 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/03
- [PULL 21/42] target/riscv: Define ePMP mseccfg,
Alistair Francis <=
- [PULL 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/03
- [PULL 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/03
- [PULL 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/03
- [PULL 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/03
- [PULL 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/03
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/03
- [PULL 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/03
- [PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/03
- [PULL 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/03
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03