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[PULL 32/42] target/riscv: fix a typo with interrupt names
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From: |
Alistair Francis |
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Subject: |
[PULL 32/42] target/riscv: fix a typo with interrupt names |
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Date: |
Tue, 4 May 2021 08:13:17 +1000 |
From: Emmanuel Blot <emmanuel.blot@sifive.com>
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bf6a00636..04ac03f8c9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
"vs_timer",
"m_timer",
"u_external",
+ "s_external",
"vs_external",
- "h_external",
"m_external",
"reserved",
"reserved",
--
2.31.1
- [PULL 22/42] target/riscv: Add the ePMP feature, (continued)
- [PULL 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/03
- [PULL 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/03
- [PULL 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/03
- [PULL 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/03
- [PULL 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/03
- [PULL 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/03
- [PULL 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/03
- [PULL 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/03
- [PULL 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/03
- [PULL 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/03
- [PULL 32/42] target/riscv: fix a typo with interrupt names,
Alistair Francis <=
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/03
- [PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/03
- [PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/03
- [PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/03
- [PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/03
- [PULL 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/03