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Re: [PULL 00/42] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/42] riscv-to-apply queue |
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Date: |
Wed, 5 May 2021 20:26:52 +0100 |
On Mon, 3 May 2021 at 23:13, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502'
> into staging (2021-05-02 16:23:05 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210504-2
>
> for you to fetch changes up to 7a98eab3a704139020bdad35bfae0356d2a31fa0:
>
> target/riscv: Fix the RV64H decode comment (2021-05-04 08:03:43 +1000)
>
> ----------------------------------------------------------------
> A large collection of RISC-V fixes, improvements and features
>
> - Clenaup some left over v1.9 code
> - Documentation improvements
> - Support for the shakti_c machine
> - Internal cleanup of the CSR accesses
> - Updates to the OpenTitan platform
> - Support for the virtio-vga
> - Fix for the saturate subtract in vector extensions
> - Experimental support for the ePMP spec
> - A range of other internal code cleanups and bug fixes
This fails building the docs:
Warning, treated as error:
/home/petmay01/linaro/qemu-for-merges/docs/system/riscv/shakti-c.rst:document
isn't included in any toctree
The new board doc file needs to be referenced from the
toctree in docs/system/target-riscv.rst .
thanks
-- PMM
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, (continued)
- [PULL 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/03
- [PULL 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/03
- [PULL 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/03
- [PULL 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/03
- [PULL 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/03
- [PULL 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/03
- [PULL 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/03
- [PULL 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/03
- Re: [PULL 00/42] riscv-to-apply queue,
Peter Maydell <=