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[PULL 02/12] hw/intc: Move sifive_plic.h to the include directory
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From: |
Alistair Francis |
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Subject: |
[PULL 02/12] hw/intc: Move sifive_plic.h to the include directory |
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Date: |
Fri, 23 Oct 2020 08:16:09 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Since sifive_plic.h is used by hw/intc/sifive_plic.c,
it has to be in the public include directory. Move it.
Fixes: 84fcf3c15111 ("hw/riscv: Move sifive_plic model to hw/intc")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1602578033-68384-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
{hw => include/hw}/intc/sifive_plic.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename {hw => include/hw}/intc/sifive_plic.h (100%)
diff --git a/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
similarity index 100%
rename from hw/intc/sifive_plic.h
rename to include/hw/intc/sifive_plic.h
--
2.28.0
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2020/10/23
- [PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask(), Alistair Francis, 2020/10/23
- [PULL 03/12] target/riscv: Fix update of hstatus.SPVP, Alistair Francis, 2020/10/23
- [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory,
Alistair Francis <=
- [PULL 05/12] target/riscv: Fix implementation of HLVX.WU instruction, Alistair Francis, 2020/10/23
- [PULL 06/12] hw/riscv: sifive_u: Allow specifying the CPU, Alistair Francis, 2020/10/23
- [PULL 08/12] hw/riscv: Add a riscv_is_32_bit() function, Alistair Francis, 2020/10/23
- [PULL 07/12] hw/riscv: Return the end address of the loaded firmware, Alistair Francis, 2020/10/23
- [PULL 09/12] hw/riscv: Load the kernel after the firmware, Alistair Francis, 2020/10/23
- [PULL 10/12] target/riscv: raise exception to HS-mode at get_physical_address, Alistair Francis, 2020/10/23
- [PULL 11/12] hw/misc/sifive_u_otp: Add write function and write-once protection, Alistair Francis, 2020/10/23
- [PULL 04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt, Alistair Francis, 2020/10/23
- [PULL 12/12] hw/misc/sifive_u_otp: Add backend drive support, Alistair Francis, 2020/10/23
- Re: [PULL 00/12] riscv-to-apply queue, Peter Maydell, 2020/10/26