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[PULL 03/12] target/riscv: Fix update of hstatus.SPVP
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From: |
Alistair Francis |
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Subject: |
[PULL 03/12] target/riscv: Fix update of hstatus.SPVP |
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Date: |
Fri, 23 Oct 2020 08:16:10 -0700 |
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
When trapping from virt into HS mode, hstatus.SPVP was set to
the value of sstatus.SPP, as according to the specification both
flags should be set to the same value.
However, the assignment of SPVP takes place before SPP itself is
updated, which results in SPVP having an outdated value.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013151054.396481-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6c68239a46..47d05fe34c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -938,7 +938,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
- get_field(env->mstatus, SSTATUS_SPP));
+ env->priv);
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
--
2.28.0
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2020/10/23
- [PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask(), Alistair Francis, 2020/10/23
- [PULL 03/12] target/riscv: Fix update of hstatus.SPVP,
Alistair Francis <=
- [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory, Alistair Francis, 2020/10/23
- [PULL 05/12] target/riscv: Fix implementation of HLVX.WU instruction, Alistair Francis, 2020/10/23
- [PULL 06/12] hw/riscv: sifive_u: Allow specifying the CPU, Alistair Francis, 2020/10/23
- [PULL 08/12] hw/riscv: Add a riscv_is_32_bit() function, Alistair Francis, 2020/10/23
- [PULL 07/12] hw/riscv: Return the end address of the loaded firmware, Alistair Francis, 2020/10/23
- [PULL 09/12] hw/riscv: Load the kernel after the firmware, Alistair Francis, 2020/10/23
- [PULL 10/12] target/riscv: raise exception to HS-mode at get_physical_address, Alistair Francis, 2020/10/23
- [PULL 11/12] hw/misc/sifive_u_otp: Add write function and write-once protection, Alistair Francis, 2020/10/23
- [PULL 04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt, Alistair Francis, 2020/10/23
- [PULL 12/12] hw/misc/sifive_u_otp: Add backend drive support, Alistair Francis, 2020/10/23